1. Field of the Invention
The invention relates generally to configurations for efficient utilization of charge-coupled devices as storage registers, and more particularly to apparatus forming a multiphase series-parallel-series (SPS) charge-coupled device (CCD) shift register.
2. Description of the Prior Art
In data processing technology, memories, devices for storage of information, are of critical importance. A recent development in this technology is that of charge-coupled devices. The basic operation of charge-coupled devices (CCDs) has been explained in detail in the technical and patent literature, but a brief summary of the operation of such devices is believed to facilitate an understanding of the present invention. While the operation of a charge-coupled device will be given in terms of specific semiconductor material types, it will be understood that in general where N-type material is specified, P-type material may be substituted and vice versa. The device can also be implemented using buried channel technology.
A typical charge-coupled device may consist of an N-type silicon substrate (in which holes are normally the minority signal carriers) with a silicon dioxide insulating layer superimposed on its surface. An arrangement of conducting electrodes is deposited on the surface of the insulator.
When clock voltages are applied to predetermined groupings of the electrodes, the holes in the vicinity of each electrode, assuming that holes are initially present (as a result, for example, of the injection into the device), will move one charge-coupled element, or unit cell, in a predetermined direction for each full clock cycle. The packets of charge move in the predetermined direction as a result of the continuous lateral displacement of the local potential well in which they find themselves. Charge-coupling is thus the collective transfer of all the mobile electric charge stored within a semiconductor storage element to a similar, adjacent storage element by the external manipulation of clock voltages.
The quanity of charge capable of being stored in the mobile packets can vary widely, depending on the applied voltages, the capacitance of the storage element, and other factors. The amount of electric charge in each packet can represent information. Charge coupled devices have utility in photosensor arrays, delay lines, shift registers, buffer memeories, sequential-access memories, fast-access scratch-pad memories, refresh memories, and other information storage and transfer mechanisms.
The focus of the present invention is not concerned with the physical structure, i.e., the internal charge transfer and charge storage positions of a charge-coupled device, no with the manufacturing processes for effecting the same. Several types of change storage and charge transfer structures are known in the art. Two such structures are described in "Staggered Oxide Conductivity Connected Charge-Coupled Device" and "Work Function Barrier Charge-Coupled Device", Related Applications Nos. 1 and 2 respectively, and may be utilized in conjunction with the present invention. These inventions permit closed row-to-row spacing and hence, a structure of higher density than some other prior art devices. They also eliminate the necessity of closely spaced electrodes and the attendant problems associated with such design, as well as reduce the power consumption and allow for relatively high operational frequency of charge-coupled devices.
The present invention is concerned with utilization of CCDs as memory devices in computer systems. Such memories are generally of two types: main memories which are characteristically fast and expensive, and auxiliary memories which are relativey slow but cheap. CCD-type memories are envisioned as a third (intermediary) memory, with particular utility as a cache memory, i.e. a buffer unit between main and auxiliary memories. In such applications, CCDs could present considerable advantages if their potential for providing high density storage can be realized. Essential to such realization is the requirement of having the highest density registers possible.
Prior art CCD applications have been generally of a serpentine configuration, which is a back-and-forth serial transfer path. Charge packets are serially transferred in a first direction through a first row. They are then sensed and amplified, and then serially transferred through the second row in the opposite direction. This sequence of operations transfer, sense and amplify, and then transfer in the opposite direction is repeated for a plurality of rows.
Alternate configurations have been suggested in the prior art including parallel and series-parallel-series (SPS) registers. However, none of the suggested configurations were capable of high density storage, which is essential to any arrangement for actual utilization of CCDs in a computer environment. This is due in part to the fact that the prior art configurations were developed primarily for applications in the optical imaging field.
The clocking for the serpentine and most other prior art configurations has been two-or three-phase clocking. In this manner, only two or three clock drivers are required, but the storage density within the CCD is far less than optimal. Two-phase clocking requires two sites (or cells) per bit of information stored, thereby utilizing only 50% of the storage capacity. Three-phase clocking requires three sites per bit. Clearly, improvement upon these storage densities is desirable. Multiphased operation of registers have been proposed in the prior art. However, they have generally been inefficient, some have required a multiplexed rhombus configuration. In the optimum, it is desirable to approach one site per bit of information. Such high density could then be directly reflected in significant cost savings in computer memories systems which utilize CCD technology. An arrangement is also needed whereby high density CCDs are designed for usage in an environment which itself is highly efficient in its spaced requirements.
Another problem with CCD storage devices in general, and the serpentine configuration in particular, is that charge is dissipated as it is transferred from cell to cell. This imposes the requirement that there can be only a limited number of transfers of the charge packets before the introduction of a refresh operation, i.e. an amplification of the charge packet. It is noted that amplifiers do not perform the essential memory function, i.e, storage. Therefore, it is desirable to minimize the number of amplifiers required per bit of storage in order to achieve a high density environment for the register.